In applications where optical signals are used to transmit data, such as fiber-optic communications systems, fast and efficient driver circuits are required for modulating the optical emission of optical transmitters such as laser diodes, light emitting diodes, vertical cavity surface emitting lasers, and similar opto-electronic devices. Where the modulation rates extend into regions where electrical reflections within interconnections between the driver circuitry and the driven opto-electronic device cannot be neglected, electrical terminations are often required.
A commonly used driver arrangement in prior art is a DC coupled driver 100 for driving a VCSEL D as shown in FIG. 1. It comprises a differential input npn bipolar transistor pair q3 and q4. Differential voltage inputs vin and vip are connected to a base on the transistors q3 and q4 to excite collector currents i3 and i4, respectively. A supply voltage Vdd is connected to a collector of the transistor q4 and through a current source I to a collector of the transistor q3. An anode of the VCSEL D receives a voltage Vd at the collector of the transistor q3 to produce a driving current iD. A cathode of the VCSEL D is connected to a circuit ground. Emitters of the transistors q3 and q4 are also connected to the circuit ground, but through a current source 2M. There is no back-termination.
The output current range is I for a ‘one’ level and I−2M for a ‘zero’ level. This prior art driver has a power dissipationPdiss=Vdd*(I+M).  Equation [1a]
This driver has a problem in that without the back termination the circuit is susceptible to signal degradation due to reflections resulting from wire-bonds which are typically used to provide a connection between the driver output Vd and the load, VCSEL D. Even when the wire-bond length is held to small values like 1 mm or less, the reflection amplitude and delay can cause significant degradation in an eye diagram on the driver output Vd. To prevent this reflection from causing severe problems, the rise and fall time of the transistors q3 and q4 must be increased, thus precluding operation at very high modulation rates.
Another prior art driver 200 shown in FIG. 2 results when a passive termination resistor P is connected between the collectors of the transistors q3 and q4. For greatest effect, the value of the passive termination resistor P is adjusted to equal a VCSEL impedance, zD. In addition, an upper current source 2M′ is inserted between the collector of the transistor q4 and the voltage supply Vdd. A by-pass capacitor Cb is provided between the circuit ground and the collector of the transistor q4.
In this circuit, the average bias in VCSEL D is set by the current source I, rather than the ‘one’ level. The ‘one’ level consists of a current (I+M) and ‘zero’ level consists of a current (I−M). While this circuit is fast and provides good eye quality, its power dissipation is higher than for the driver 100 in FIG. 1:Pdiss=Vdd*(I+2M).  Equation [1b]
This driver circuit can maintain a nearly constant power supply current, with small transient spikes occurring at the data transitions.
However, it has a problem in that for a large current M and high VCSEL voltage or impedance, a typical 3.3V power supply voltage is insufficient, as too much voltage is dropped across the passive termination resistor P. That leaves too little voltage for the upper current source 2M′ to operate properly when the VCSEL voltage is high.
Another drawback stems from difficulties in handling long consecutive identical digit (CID) data streams. Since node Vr is supplied by a current source rather than a voltage source, its DC value can drift in the presence of CID. The most practical way to prevent this problem from being severe is to use large values of the by-pass capacitor Cb, but this is costly in terms of integrated circuit die area. Still, well designed circuits of this type may see ‘one’ or ‘zero’ levels shift by up to 10% in the presence of 50 CIDs.
To reduce the severity of this problem, the current source 2M can be augmented with a shunt amplifier to the circuit ground. However the DC value drift is reduced at the expense of higher power dissipation. A prior art driver 300 shown in FIG. 3 was designed to overcome the shortcomings of the driver 100 in FIG. 1 by removing constraints on the Vdd, as well as including an active back termination but with reduced power dissipation.
An additional differential bipolar transistor pair q5, q6 is driven by the same differential voltage inputs vin and vip as the differential pair q3, q4, respectively, to create a voltage at node V3 which tracks the voltage at Vd. The emitters of the transistors q5, q6 are connected to the circuit ground through an augmenting current source 2A. A unity gain follower x1 buffers voltage V3 and drives a resistor S, which provides the termination impedance. The value of the resistor S can be partially or fully provided by the inherent output impedance of unity gain follower x1. The voltage generated across resistor T by current i5 is chosen to track the voltage Vd such that V3 and Vd track each other. Since V3 and Vd are ideally always equal, no current flows through the resistor S. A bias loop including a low speed operational amplifier U4 drives a gate of a PMOS FET mr to produce a voltage Vr at a drain of the PMOS FET mr to ensure that the average current in S is near zero. The power dissipation of this circuit is:Pdiss=Vdd*(I+M+2A+i(x1)),  Equation [1c]
where i(x1) is the current drawn by unity gain follower x1, I, M, 2A are currents in the current sources I, 2M, 2A and Vdd is a power supply voltage.
This is typically higher than for driver 100 of FIG. 1 but less than for driver 200 of FIG. 2.
As in the other prior art, the supply current drawn by the driver 300 is not constant, so possibilities of cross-talk and electromagnetic interference exist. The headroom to supply voltage Vdd is greater in this prior art driver 300 than that of the driver 200 in FIG. 2. Typically the voltage Vr is higher than the voltage Vd by a factor of T*A, which may be several hundred millivolts. Also, if the voltage difference Vdd−Vr drops below several hundred millivolts, the PMOS FET mr will cease to function as a current source. Typically, these factors confine the supply voltage to Vdd>3V and the diode voltage to Vd<2.2V in the bipolar case, thereby limiting the operating range and selection of the VCSEL D, leading to a great loss in accuracy as these limits are neared and current sources start to saturate.
Another problem present in prior art driver 300 is that due to a group delay in the unity gain follower x1 and mismatched time constants at circuit nodes V3 and Vd, the dynamic voltage at node V4 always lags the voltage at node Vd. At 10 Gbps data rates with a 100 pS bit period, this lag, typically 10 ps, can be severe. It slows the rise and fall time at node Vd, since during slewing, the output drive current iD is stolen because the current in resistor S does not equal zero.
Another problem with the prior art driver 300 stems from the voltage Vr being supplied from a current source comprising the PMOS FET mr. Thus, if long CIDs are present in the input signal stream, the value of voltage Vr will drift with a bias loop time constant. The only way to prevent this problem from being severe is to use large values of by-pass capacitor Cb, but this is costly in terms of die area. Nonetheless, well designed circuits of this type may see ‘one’ or ‘zero’ levels shift by up to 5% in the presence of 50 CIDs. A shunt voltage regulator can also be added in parallel with the current source to overcome this, but at the expense of increased power dissipation.
In FIG. 4 a further example of a prior art VCSEL driver 400 is shown, which possesses a very low power dissipation given by:Pdiss=Vcc*Im+Vdd*Ib.  Equation [1d]
Differential voltage inputs vip and vin are each connected to a gate on a differential input NMOS field-effect transistor (FET) pair mp and mn, respectively, each of whose drain is connected to a first supply voltage Vcc through a load resistor Rc. Sources of the transistors mp and mn are connected together to a modulation current source Im working into the ground connection. The cathode of a diode D (such as a VCSEL) is connected to the drain of transistor mn, while its anode is driven by a bias current source Ib from a second supply voltage Vdd. The anode of the VCSEL D is AC grounded through a bypass capacitor Cg.
The differential voltage inputs vip and vin are driven so as to switch all of current Im into the load resistor Rc on the left or into the parallel combination of load resistor Rc on the right and the VCSEL diode D. The average or bias current in diode D is just the upper current source current Ib. At high modulation rates, where the bypass capacitor Cg acts like an AC short circuit, the current in diode D will be:Id=Ib±Im*Rc/(zD+Rc),  Equation [1e]
where zD is the impedance of the diode D.
Baseline wander is a bias shift away from a statistical 50/50 ‘one’ level to ‘zero’ level balance. Problems occur with the VCSEL driver 400 when data fed to inputs vip, vin does not maintain the 50/50 balance of ‘one’ level/‘zero’ in the long term, or where there are long sequences of CIDs that shift a DC balance over a relatively long period of time.
The time constant of this circuit is:tc=Cg*Rc∥zD,  Equation [1f]
where ∥ denotes the parallel value of impedance formed by resistor Rc and diode impedance zD. Since this forms a single pole response, then for a constant vip−vin input voltage, the current through diode D will settle to the current Ib from the starting point of Ib±Im*Rc/(zD+Rc) after approximately 2.2 time constants. Consider an example where this VCSEL driver 400 is designed to operate at 10 Gbps.
Typically, to keep the baseline wander small, a design may specify that a low frequency −3 dB corner of the driver circuit 400 be less than 300 kHz. For the parallel value of impedance Rc∥zD equal to 70 ohm, the value of Cg required to achieve this is:Cg=1/((Rc∥zD)*2π*300 kHz)=7.6 nF.  Equation [1g]
This amount of capacitance is much larger than a reasonable amount of capacitance available in a typical integrated circuit process. In many applications it is not feasible to use an off-chip capacitor because of the parasitics encountered in going off chip, or because there is no room for such a capacitor. Hence the 300 kHz low frequency corner cannot be achieved, and this circuit would not be usable for 10 Gbps or lower data rates where 231−1 pseudo-random bit sequence (PRBS) data is present.
If, for example, even the large value of 0.1 nF of on-chip capacitance could be provided for Cg, then the time constant of this circuit would be 0.1 nF*70 ohms=7 ns. If the input data were a 231−1 PRBS, where 31 CIDs are occasionally encountered, then such a CID event would last about 3.1 ns. In that amount of time the DC value of the current in diode D can shift by nearly 10%.
Additionally, the worst case imbalance occurs when the running digital sum reaches its maximum, in which case the DC shift is even greater. This amount of DC shift, or baseline wander could not be tolerated in a VCSEL driver application.
A final prior art common anode VCSEL driver 500 is shown in FIG. 5. The magnitude of the differential driving voltage |vip−vin| should be large enough to allow complete switching of the modulation current im between transistors mp and mn. The anode of the VCSEL diode D is connected to a positive supply voltage Vdd, while its cathode is biased by a bias current source iz from the circuit ground so that a minimum of the diode current iD, or ‘zero’ level current is provided just above a threshold of the VCSEL diode D. When the input vip sufficiently exceeds the voltage at input vin, all of the modulation current im is switched through transistor mp, increasing the diode current iD to im+iz=io, or the ‘one’ level current.
When vin exceeds vip and current im is switched through transistor mn, then the VCSEL current iD=iz. The VCSEL forward voltage drop typically ranges from 1.6 V at currents just above threshold to 2.2 V at higher currents typical of the one level current. Therefore, to allow approximately 1 V at the drain of transistor mp, Vdd will typically be 3V or greater. Vcc may be equal to Vdd, or it could be lower, around 1 V, to reduce power dissipation and prevent large Vds at transistor mn. Under typical conditions where the duty cycle of vip and vin is 50%, the power dissipation of the driver 500 is given by Equation 1h, which is typically the lowest power dissipation of any type of VCSEL driver.Pdiss=0.5*im*(Vcc+Vdd)+iz*Vdd  Equation [1h]
This type of circuit 500 is also capable of operation at very high data rates. At data rates greater than 10 Gbps it is very important that the distance between the driver circuitry, typically located on an integrated circuit, be very close to the VCSEL diode which is separate from the driver integrated circuit and connected to it by means of a wire-bond or printed circuit trace on a printed circuit board. Keeping this distance short is important to ensure that reflections caused by impedance mismatches between the high output impedance of the VCSEL driver and the much lower impedance of the VCSEL can be attenuated quickly. If the distance between the two is large, then the reflections from the impedance mismatches will reverberate back and forth between the two ends of the wire-bond or printed circuit trace for long periods of time, potentially interfering with subsequent data values.
A DC coupled driver for driving an optoelectronic emitter such as a vertical cavity surface emitting laser (VCSEL) is presented, which overcomes the shortcomings of the described prior art.
It is an object of the invention to provide a DC-coupled driver for high speed modulation of a VCSEL with improved immunity to pulse reflections in the interconnect between the driver and the VCSEL by incorporating an active termination.
A further object of the invention is to define different integrated circuit technologies for the DC-coupled driver, which are suitable for large scale manufacturing, including npn bipolar transistor and CMOS (NMOS and PMOS) technologies.
Another object of the invention is to achieve a low total power dissipation for the driver.
Provision is also made for using the active termination to control rise and fall times of the driver by adding a time delayed component of the input signal.